A frequency synthesizer adopts a technique that enables the use of a decimal fraction in setting a frequency when the frequency is not an integer multiple of a value resulting from dividing a reference frequency for setting the frequency by an integer. The most typical technique is a fractional N frequency synthesizer. As disclosed in, for example, Unexamined Japanese Patent Application Kokai Publication No. 2009-130760, this technique is utilized to increase the frequency resolution of the digital portion, thereby enabling fine decimal fraction frequency division setting.
A fractional N frequency synthesizer includes a reference frequency oscillator, a phase frequency comparator (PFC), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), a multi-modulus frequency divider, and a ΔΣ modulator.
The phase frequency comparator compares the reference frequency output from the reference frequency oscillator with the phase frequency of an input signal and outputs the difference between the reference frequency and the phase frequency. A pulse signal output from the CP in accordance with the output of the phase frequency comparator is smoothed by the loop filter and serves as the control voltage for the VCO. This control voltage controls the oscillating frequency of the VCO. The VCO outputs a clock signal having a frequency proportional to the control voltage.
The ΔΣ modulator accumulates the fractional set value at each reference frequency cycle, and generates a carryover signal when the accumulated value exceeds the maximum value of an accumulator in the ΔΣ modulator. The multi-modulus frequency divider divides the frequency of the clock signal from the VCO by a different frequency division value depending on whether the carryover signal is generated by the ΔΣ modulator at each reference frequency cycle, and uses the clock signal with the divided frequency as the input signal to the phase frequency comparator.
With the fractional set value of the ΔΣ modulator being changed, the fractional N frequency synthesizer can generate not only a frequency that is an integer multiple of the value resulting from dividing the reference frequency by an integer but also generate a frequency that is a decimal fraction multiple of the value. In such a case, the operation cycle of the ΔΣ modulator (the timing for performing iterative accumulation) is equal in length to the cycle of division by N or division by N+1 executed by the multi-modulus frequency divider.